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The Fetch-Execute Cycle

FoundationHigherAQA

Practise The Fetch-Execute Cycle for GCSE Computer Science with this free worksheet and full mark scheme — Foundation and Higher exam-style questions with worked answers. The CPU continually fetches an instruction, decodes it and then executes it.

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These worksheets and mark schemes are original, written for Virtus Academy and checked against the current AQA specification. Every worksheet comes with a full mark scheme.

Foundation

WorksheetFoundation · PDFMark SchemeFoundation · PDF

Higher

WorksheetHigher · PDFMark SchemeHigher · PDF

Topic overview

The fetch-execute cycle is the sequence the CPU repeats continuously to run a program.

In the fetch stage, the address in the program counter is copied to the memory address register. The instruction at that address is fetched from main memory into the memory data register. The program counter is then incremented so it points to the next instruction.

In the decode stage, the control unit works out what the instruction means and which components are needed. In the execute stage, the instruction is carried out — a calculation in the ALU, a value written to memory, or data moved between registers. The cycle then repeats, which is why a computer runs continuously rather than in bursts.

Revision notes

The fetch stage

The address in the program counter is copied into the memory address register.

The instruction at that address is fetched from main memory into the memory data register. The program counter is incremented so it points to the next instruction.

The decode stage

The control unit examines the instruction and works out what it means.

It determines which operation is required and which components will be needed — the ALU for a calculation, or memory access for a load or store.

The execute stage

The instruction is carried out.

This may be a calculation performed by the ALU with the result placed in the accumulator, a value written to memory, or data moved between registers. The cycle then begins again.

Key points

  • The cycle is fetch, decode, execute.
  • The program counter address goes to the MAR.
  • The instruction is fetched into the MDR.
  • The program counter is then incremented.
  • The control unit decodes the instruction.
  • The cycle repeats continuously.

Worked examples

Example 1

Describe the fetch stage of the fetch-execute cycle. [3 marks]

Working

The address in the program counter is copied into the memory address registerstate the first step
The instruction at that address is fetched from main memory into the memory data registerstate the second step
The program counter is incremented so it points to the next instructionstate the third step

Example 2

Explain why the program counter is incremented during the fetch stage. [2 marks]

Working

It must point to the next instruction ready for the following cyclestate the purpose
so the CPU works through the program in order rather than repeating the same instructionexplain the consequence

Example 3

State what happens during the decode stage. [2 marks]

Working

The control unit examines the instruction to work out what it meansstate what happens
and determines which components are needed to carry it outstate the outcome

Common mistakes

  • Incrementing the program counter at the wrong stage.

    It happens during fetch, after the address has been used.

  • Confusing the MAR and MDR in the sequence.

    The address goes to the MAR; the instruction comes back into the MDR.

  • Saying the ALU decodes instructions.

    The control unit decodes; the ALU executes calculations.

  • Giving only two stages.

    Fetch, decode and execute are all required.

Exam tips

  • Describe the fetch stage as three ordered steps.
  • Say the program counter is incremented during fetch.
  • Keep MAR and MDR the right way round.
  • Name the control unit as the decoder.

Key terms

Fetch-execute cycle
The sequence the CPU repeats to run a program.
Program counter
The register holding the next instruction's address.
Memory address register
The register holding the address being accessed.
Memory data register
The register holding the data or instruction fetched.

Related topics

Written and reviewed against the current AQA specification. Spotted an error? Let us know.